Verilog Structured procedures

All procedures in the Verilog HDL are specified within one of the following four statements:
— initial construct
— always construct
— Task
— Function
The initial and always constructs are enabled at the beginning of a simulation. The initial construct shall
execute only once, and its activity shall cease when the statement has finished. In contrast, the always
construct shall execute repeatedly. Its activity shall cease only when the simulation is terminated. There
shall be no implied order of execution between initial and always constructs. The initial constructs need not be scheduled and executed before the always constructs. There shall be no limit to the number of initial and always constructs that can be defined in a module.
Tasks and functions are procedures that are enabled from one or more places in other procedures. Tasks and functions are described in (<add link>).

Initial construct:

The following example illustrates use of the initial construct for initialization of variables at the start of
simulation-

initial begin
      areg = 0; // initialize a reg
      for (index = 0; index < size; index = index + 1)
          memory[index] = 0; //initialize memory word
end

Another typical usage of the initial construct is specification of waveform descriptions that execute once to provide stimulus to the main part of the circuit being simulated.

initial begin
      inputs = 'b000000; // initialize at time zero
      #10 inputs = 'b011001; // first pattern
      #10 inputs = 'b011011; // second pattern
      #10 inputs = 'b011000; // third pattern
      #10 inputs = 'b001000; // last pattern
end

Always construct:

The always construct, because of its looping nature, is only useful when used in conjunction with some form of timing control. If an always construct has no control for simulation time to advance, it will create a
simulation deadlock condition.
The following code, for example, creates a zero-delay infinite loop:
always areg = ~areg;
Providing a timing control to the above code creates a potentially useful description as shown in the
following:
always #half_period areg = ~areg;

<< Previous | Next >>