Verilog nonblocking procedural assignment

The nonblocking procedural assignment allows assignment scheduling without blocking the procedural
flow. The nonblocking procedural assignment statement can be used whenever several variable assignments within the same time step can be made without regard to order or dependence upon each other.

The nonblocking assignment operator is the same operator as the less-than-or-equal-to relational operator. The interpretation shall be decided from the context in which <= appears. When <= is used in an expression, it shall be interpreted as a relational operator; and when it is used in a nonblocking procedural assignment, it shall be interpreted as an assignment operator.

The nonblocking procedural assignments shall be evaluated in two steps as discussed in Scheduling semantics(<add link>). These
two steps are shown in the following example:

Example 1:
module evaluates2 (out);
output out;
reg a, b, c;
initial begin
    a = 0;
    b = 1;
    c = 0;
end
always c = #5 ~c;
always @(posedge c) begin
    a <= b; // evaluates, schedules,
    b <= a; // and executes in two steps
end
endmodule

Below are steps to execute above example:
1) .At posedge c, the simulator evaluates the right-hand sides of the nonblocking assignments and schedules the assignments of the new values at the end of the nonblocking assign update events.
2). When the simulator activates the nonblocking assign update events, the simulator updates the left-hand side of each nonblocking assignment statement.

Example 2
//non_block1.v
module non_block1;
reg a, b, c, d, e, f;
//blocking assignments
initial begin
    a = #10 1; // a will be assigned 1 at time 10
    b = #2 0; // b will be assigned 0 at time 12
    c = #4 1; // c will be assigned 1 at time 16
end
//non-blocking assignments
initial begin
    d <= #10 1; // d will be assigned 1 at time 10
    e <= #2 0; // e will be assigned 0 at time 2
    f <= #4 1; // f will be assigned 1 at time 4
end
endmodule

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