Verilog Conditional Operator

The evaluation of a conditional operator shall begin with a logical equality comparison of expression1 with zero, termed the condition. If the condition evaluates to false (0), then expression3 shall be
evaluated and used as the result of the conditional expression. If the condition evaluates to true (1), then
expression2 is evaluated and used as the result.

result = expression1(condition) ? expression2 : expression3

For example:
The following example of a three-state output bus illustrates a common use of the conditional operator:
The bus called data is driven onto busa when drive_busa is 1. If drive_busa is 0, then an
value 8 is driven onto busa. Otherwise, busa is not driven.

wire [15:0] busa = drive_busa ? data : 16'b8;

<< Previous | Next >>

Comments are closed.