VERILOG

Data Types
Operators & Operands
Scheduling Semantics

Assignments
Gate modelling
Behavioral modeling

Tasks and Functions
Compiler Directives
Code Examples

SYSTEM VERILOG

Data types
Data Declarations
Operators and Expressions
Procedural Statements and Control Flow

Processes
Tasks & Functions
Classes
Random Constraints
Clocking Blocks

Program Block
Assertions
Interfaces
Coverage
Parameters

UVM

UVM Testbench Architecture
Factory
Phasing
Configuration

Transaction-Level Modeling
Verification Components
Sequences

Register layer classes
Callbacks
Macros in UVM