Verilog behavioral models contain procedural statements that control the simulation and manipulate
variables of the data types previously described. These statements are contained within procedures. Each
procedure has an activity flow associated with it.
The activity starts at the control constructs initial and always. Each initial construct and each always
construct starts a separate activity flow. All of the activity flows are concurrent to model the inherent
concurrence of hardware.
The following example shows a complete Verilog behavioral model-
module behave;
reg [1:0] a, b;
initial begin
a = 'b1;
b = 'b0;
end
always begin
#50 a = ~a;
end
always begin
#100 b = ~b;
end
endmoduleDuring simulation of this model, all of the flows defined by the initial and always constructs start together at simulation time zero. The initial constructs execute once, and the always constructs execute repetitively.
In this model, the reg variables a and b initialize to 1 and 0, respectively, at simulation time zero. The initial construct is then complete and does not execute again during this simulation run. This initial construct contains a begin-end block (also called a sequential block) of statements. In this begin-end block, a is initialized first, followed by b.
The always constructs also start at time zero, but the values of the variables do not change until the times
specified by the delay controls (introduced by #) have elapsed. Thus, reg a inverts after 50 time units and
reg b inverts after 100 time units. Because the always constructs repeat, this model will produce two square waves. The reg a toggles with a period of 100 time units, and reg b toggles with a period of 200 time units.
The two always constructs proceed concurrently throughout the entire simulation run.
Procedural assignments:
Procedural assignments are used for updating reg, integer, time, real, realtime,
and memory data types. There is a significant difference between procedural assignments and continuous assignments:
— Continuous assignments drive nets and are evaluated and updated whenever an input operand
changes value.
— Procedural assignments update the value of variables under the control of the procedural flow
constructs that surround them.
The right-hand side of a procedural assignment can be any expression that evaluates to a value. The lefthand side shall be a variable that receives the assignment from the right-hand side. The left-hand side of a procedural assignment can take one of the following forms:
— reg, integer, real, realtime, or time data type: an assignment to the name reference of one of these
data types.
— Bit-select of a reg, integer, or time data type: an assignment to a single bit that leaves the other bits
untouched.
— Part-select of a reg, integer, or time data type: a part-select of one or more contiguous bits that
leaves the rest of the bits untouched.
— Memory word: a single word of a memory.
— Concatenation or nested concatenation of any of the above: a concatenation or nested concatenation
of any of the previous four forms. Such specification effectively partitions the result of the righthand
expression and assigns the partition parts, in order, to the various parts of the concatenation or
nested concatenation.
The Verilog HDL contains two types of procedural assignment statements:
— Blocking procedural assignment statements
— Nonblocking procedural assignment statements
Blocking and nonblocking procedural assignment statements specify different procedural flows in
sequential blocks.