Introduction of Verilog Tasks and functions

Tasks and functions provide the ability to execute common procedures from several different places in a
description. They also provide a means of breaking up large procedures into smaller ones to make it easier to read and debug the source descriptions. This topic discusses the differences between tasks and functions, describes how to define and invoke tasks and functions, and presents examples of each.

Difference between tasks and functions:

The following rules distinguish tasks from functions:
— A function shall execute in one simulation time unit; a task can contain time-controlling statements.
— A function cannot enable a task; a task can enable other tasks and functions.
— A function shall have at least one input type argument and shall not have an output or inout type
argument; a task can have zero or more arguments of any type.
— A function shall return a single value; a task shall not return a value.

The purpose of a function is to respond to an input value by returning a single value. A task can support
multiple goals and can calculate multiple result values. However, only the output or inout type arguments
pass result values back from the invocation of a task. A function is used as an operand in an expression; the value of that operand is the value returned by the function.

We will discussing more details about functions & calling function in below link-
Verilog function & function calling

More Details about Task & calling task can be find in below link-
Verilog task & calling

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