The case statement is a multiway decision statement that tests whether an expression matches one of a
number of other expressions and branches accordingly. The case statement has the syntax shown in below-
case ( expression )
case_item { case_item } endcase
| casez ( expression )
case_item { case_item } endcase
| casex ( expression )
case_item { case_item } endcase
The case expression and the case item expression can be computed at run time; neither expression is
required to be a constant expression.
For Example 1:
The following example illustrates the use of a case statement to handle x and z values properly:
case (select[1:2])
2’b00: result = 0;
2’b01: result = flaga;
2’b0x,
2’b0z: result = flaga ? ‘bx : 0;
2’b10: result = flagb;
2’bx0,
2’bz0: result = flagb ? ‘bx : 0;
default result = ‘bx;
endcase
In above example, if select[1] is 0 and flaga is 0, then even if the value of select[2] is x or z, result should be 0—which is resolved by the third case.
The following example shows another way to use a case statement to detect x and z values.
case (sig)
1'bz: $display("signal is floating");
1'bx: $display("signal is unknown");
default: $display("signal is %b", sig);
endcaseCase statement with do-not-cares:
Two other types of case statements are provided to allow handling of do-not-care conditions in the case
comparisons. One of these treats high-impedance values (z) as do-not-cares, and the other treats both
high-impedance and unknown (x) values as do-not-cares.
These case statements can be used in the same way as the traditional case statement, but they begin with
keywords casez and casex, respectively.
Do-not-care values (z values for casez, z and x values for casex) in any bit of either the case expression or
the case items shall be treated as do-not-care conditions during the comparison, and that bit position shall not be considered. The do-not-care conditions in case expression can be used to control dynamically which bits should be compared at any time.
For Example —The following is an example of the casez statement. It demonstrates an instruction decode, where values of the most significant bits select which task should be called. If the most significant bit of reg_sel is a 1, then the task instruction1 is called, regardless of the values of the other bits of reg_sel.
reg [7:0] reg_sel;
casez (reg_sel)
8'b1???????: instruction1(reg_sel);
8'b01??????: instruction2(reg_sel);
8'b00010???: instruction3(reg_sel);
8'b000001??: instruction4(reg_sel);
endcase