Introduction of Verilog Tasks and functions

Tasks and functions provide the ability to execute common procedures from several different places in a
description. They also provide a means of breaking up large procedures into smaller ones to make it easier to read and debug the source descriptions. This topic discusses the differences between tasks and functions, describes how to define and invoke tasks and functions, and presents examples of each.

Difference between tasks and functions:

The following rules distinguish tasks from functions:
— A function shall execute in one simulation time unit; a task can contain time-controlling statements.
— A function cannot enable a task; a task can enable other tasks and functions.
— A function shall have at least one input type argument and shall not have an output or inout type
argument; a task can have zero or more arguments of any type.
— A function shall return a single value; a task shall not return a value.

The purpose of a function is to respond to an input value by returning a single value. A task can support
multiple goals and can calculate multiple result values. However, only the output or inout type arguments
pass result values back from the invocation of a task. A function is used as an operand in an expression; the value of that operand is the value returned by the function.

We will discussing more details about functions & calling function in below link-
Verilog function & function calling

More Details about Task & calling task can be find in below link-
Verilog task & calling

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Verilog Continuous assignments

Continuous assignments shall drive values onto nets, both vector and scalar. This assignment shall occur
whenever the value of the right-hand side changes. Continuous assignments provide a way to model
combinational logic without specifying an interconnection of gates. Instead, the model specifies the logical expression that drives the net.

The net declaration assignment:.
The first two alternatives in the net declaration are discussed in Nets and variables(<add link>). The third alternative, the net declaration assignment, allows a continuous assignment to be placed on a net in the same statement that declares the net.
For example:
The following is an example of the net declaration form of a continuous assignment:

wire (strong1, pull0) mynet = enable ;

The continuous assignment statement:
The continuous assignment statement shall place a continuous assignment on a net data type. The net may be explicitly declared or may inherit an implicit declaration in accordance with the implicit declaration rules defined in Implicit declarations Assignments on nets shall be continuous and automatic. In other words, whenever an operand in the right hand expression changes value, the whole right-hand side shall be evaluated. If the new value is different from the previous value, then the new value shall be assigned to the left-hand side.

For example:
The following example describes a module with one 16-bit output bus. It selects between one of
four input busses and connects the selected bus to the output bus.

module select_bus(busout, bus0, bus1, bus2, bus3, enable, s);
 parameter n = 16;
 parameter Zee = 16'bz;
 output [1:n] busout;
 input [1:n] bus0, bus1, bus2, bus3;
 input enable;
 input [1:2] s;
 tri [1:n] data;
 // net declaration
 // net declaration with continuous assignment
 tri [1:n] busout = enable ? data : Zee;
 // assignment statement with four continuous assignments
 assign
 data = (s == 0) ? bus0 : Zee,
 data = (s == 1) ? bus1 : Zee,
 data = (s == 2) ? bus2 : Zee,
 data = (s == 3) ? bus3 : Zee;
 endmodule

The following sequence of events is experienced during simulation of this example:
a) The value of s, a bus selector input variable, is checked in the assign statement. Based on the value
of s, the net data receives the data from one of the four input buses.
b) The setting of data net triggers the continuous assignment in the net declaration for busout. If
enable is set, the contents of data are assigned to busout; if enable is 0, the contents of Zee are
assigned to busout.

Delays:
A delay given to a continuous assignment shall specify the time duration between a right-hand operand
value change and the assignment made to the left-hand side. If the left-hand references a scalar net, then the delay shall be treated in the same way as for gate delays; that is, different delays can be given for the output rising, falling, and changing to high impedance (see Gate- and switch-level modeling <add link>).

If the left-hand references a vector net, then up to three delays can be applied. The following rules determine
which delay controls the assignment:
— If the right-hand side makes a transition from nonzero to zero, then the falling delay shall be used.
— If the right-hand side makes a transition to z, then the turn-off delay shall be used.
— For all other cases, the rising delay shall be used.
Specifying the delay in a continuous assignment that is part of the net declaration shall be treated differently
from specifying a net delay and then making a continuous assignment to the net. A delay value can be
applied to a net in a net declaration, as in the following example:

wire #10 wireA;

This syntax, called a net delay, means that any value change that is to be applied to wireA by some other
statement shall be delayed for ten time units before it takes effect. When there is a continuous assignment in a declaration, the delay is part of the continuous assignment and is not a net delay. Thus, it shall not be added to the delay of other drivers on the net.

Strength:

The driving strength of a continuous assignment can be specified by the user.
A drive strength specification shall contain one strength value that applies when the value being assigned to the net is 1 and a second strength value that applies when the assigned value is 0. 

The following keywords shall specify the strength value for an assignment of 1:
supply1 strong1 pull1 weak1 highz1
The following keywords shall specify the strength value for an assignment of 0:
supply0 strong0pull0 weak0 highz0

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Verilog Bitwise Operators

The bitwise operators shall perform bitwise manipulations on the operands; that is, the operator shall
combine a bit in one operand with its corresponding bit in the other operand to calculate 1 bit for the result.

Below are the results for each possible combinations

1 Bitwise binary AND operator:

2. Bitwise binary OR operator:

3. Bitwise binary exclusive or operator

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Verilog Logical Operators

The operators logical and (&&) and logical or (||) are logical connectives. The result of the evaluation of a logical comparison shall be 1 (defined as true), 0 (defined as false), or, if the result is ambiguous, the unknown value (x). The precedence of && is greater than that of ||, and both are lower than relational and equality operators. 

A third logical operator is the unary logical negation operator (!). The negation operator converts a nonzero or true operand into 0 and a zero or false operand into 1. An ambiguous truth value remains as x.

Example 1—If reg alpha holds the integer value 237 and beta holds the value zero, then the following
examples perform as described:
regA = alpha && beta; // regA is set to 0
regB = alpha || beta; // regB is set to 1

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Verilog Equality Operators

All four equality operators shall have the same precedence.

For the logical equality and logical inequality operators (== and !=), if, due to unknown or high-impedance bits in the operands, the relation is ambiguous, then the result shall be a 1-bit unknown value (x). 

For the case equality and case inequality operators (=== and !==), the comparison shall be done just as it is in the procedural case statement (see 9.5). Bits that are x or z shall be included in the comparison and shall match for the result to be considered equal. The result of these operators shall always be a known value, either 1 or 0.

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Verilog Operators and Operands

We will understand the various Verilog operators and operands, their types, and their applications in digital circuit design.
Verilog operators are symbols that represent computations or operations on operands. They are classified into several categories based on their functionality.

Arithmetic operators:
Arithmetic operators perform mathematical operations on operands. Common arithmetic operators in Verilog such as addition, subtraction, multiplication, division, and modulus.

reg [3:0] result;
reg [3:0] a = 3;
reg [3:0] b = 5;
always @* begin
    result = a + b;   // Addition
    result = a - b;   // Subtraction
    result = a * b;   // Multiplication
    result = a / b;   // Division
    result = a % b;   // Modulus
end

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