Que 21: What are features you will verify for a Register?
Ans 21:
We need to verify the following features in a Register verification:

  • Reset values of the register.
  • We can write and read back the same value.
  • We can write hAA,h55, h00 andhFF data to ensure no connected bits.
  • Write to the register and backdoor read from a register to ensure writing at the same address.
  • Other features are clear on read and clear on write.

Que 22: How a UVM driver is connected with a UVM sequencer?
Ans 22:
The UVM driver class contains a TLM port called uvm_seq_item_pull_port which is connected to a uvm_seq_item_pull_export of UVM sequencer in the connect phase of a UVM agent.

Que 23: What is an analysis port? What is the use of an analysis port? What are the different types of analysis ports?
Ans 23:
Analysis port (class uvm_tlm_analysis_port) — a specific type of transaction-level port that can be connected to zero, one, or many analysis exports and through which a component may call the method write implemented in another component, specifically a subscriber.
port, export, and imp classes used for transaction analysis.
Broadcasts a value to all subscribers implementing a uvm_analysis_imp.
Receives all transactions broadcasted by a uvm_analysis_port.
Exports a lower-level uvm_analysis_imp to its parent.

Que 24: What are assertions? What are the different types of assertions?
Ans 24:
Assertions are used to check the behavior of a design, It is written in the form of properties that should be true throughout the simulation. Assert property is used to activate the property and cover property is used to check if the property is getting covered. There are two types of immediate assertions and concurrent assertions. Immediate Assertions: Immediate assertions are procedural statements and are mainly used in simulation. An assertion is basically a statement that something must be true, similar to the if statement. Concurrent Assertions: These validate the circuit behavior throughout the simulation, It gets evaluated based on the clock trigger.

Que 25: What is the use of the “dist” keyword in constraint? What is the difference between “:/” and “:=” symbols in constraints?
Ans 25:
The “dist” keyword is used for distribution in constraints. It is used when we need to assign different weights to the elements of random variables. eg.: A dist { 5 := 1; [10:12] := 2 ; [15:16] :/ 2 }
Two symbols used with dist keyword “:=” assign mention weightage to each element and “/=” assigns the mention weightage divided by the number of variables. In the above example, The weightage for each element will be 5 -> 1, 10 -> 2, 11 -> 2, 12 -> 2, 15 -> 2/2, 16 -> 2/2.

Que 26: What is UVM? What is the advantage of UVM?
Ans 26:
UVM is a methodology used for functional verification.

  • Reusability through test bench
  • Plug & Play of verification Ips
  • Generic Testbench Development
  • Sequence-based stimulus generation
  • Vendor & Simulator Independent
  • Smart Test bench i.e. generate legal stimulus from pre-planned coverage plan
  • Support CDV –Coverage-Driven Verification
  • Support CRV –Constraint Random Verification
  • Register modeling

Que 27: What is the difference between “uvm_component” and “uvm_object”?
Ans 27:
“uvm_component” is used to construct the UVM environment fixed part. They are used to make testbench components that do not change throughout the simulation. Classes are registered with the factory using macro uvm_component_utils. “uvm_object” is used for UVM transient objects like uvm_seq_item, uvm_transaction, and uvm_sequence. The base class uvm_object is also used for configuration objects, i.e. classes that contain configuration data to configure uvm_components, sequences, etc. Classes are registered with the factory using macrouvm_object_utils.

Que 28: What is uvm_phase? What are the different phases in UVM?
Ans 28:
UVM phases act as a synchronizing mechanism in the simulation because phases are defined as callbacks, classes derived from uvm_component can perform useful work in the callback phase method. Different phases in UVM are :

  • build_phase
  • connect_phase
  • end_of_elaboration_phase
  • start_of_simulation_phase
  • run_phase
  • extract_phase
  • check_phase
  • report_phase

Sub-phases in run_phase are :

  • reset_phase
  • configure_phase
  • main_phase
  • shutdown_phase

Que 29: Which UVM phase is top-down, bottom–up & parallel?
Ans 29:
The build phase is top-down and the Run phase is a parallel phase as all the run phases run parallelly. All other phases are bottom-up.

Que 30: Which phase is the task/time-consuming phase?
Ans 30:
The run phase is a task in UVM, while all other phases are functions, so the only Run phase is a time-consuming phase.

<< Previous | Next >>


Que 11: Write a code to generate a 100MHz clock.
Ans 11:
To generate a 100MHz clock, which is a 10ns time period. We can write the below code.

module clk_100M ;
reg clk ;
initial begin
clk = 0;
forever #5ns clk = !clk ;

Que 12: What is a clocking block, What are the uses of a clocking block?
Ans 12: A clocking block is a set of signals synchronized on a particular clock. It basically separates the time-related details from the structural, functional, and procedural elements of a test bench. It helps the designer develop test benches in terms of transactions and cycles.

Que 13: Write a code to generate a 10MHz clock with a 60% duty cycle.
Ans 13:
To generate a 10MHz clock, which is a 100ns time period. We can write the below code.

module clk_10M_60D ;
reg clk ;
initial begin
clk = 0 ;
forever begin
40ns clk = !clk ;
60ns clk = !clk ; end
end endmodule

Que 14: Write a code to generate two clocks of 10Mhz with 90o Phase shift.
Ans 14: To generate a 10MHz clock, which is a 100ns time period. To shift the 90o phase of the second clock we can delay the second clock by 100ns x 360o/ 90o.

module clk_10M_90d ;
reg clk1 , clk2 ;
initial begin
clk1 = 0 ;
50ns clk1 = !clk1 ;
initial begin
clk2 = 0 ;
25ns ;
50ns clk2 = !clk2 ;
end endmodule

Que 15: What are the steps in digital verification flow?
Ans 15:
The main steps involved in digital verification are as follows:

  • Verification Plan: The verification plan involves the feature extraction from the DUT and plans test cases to verify each feature. It also specifies the coverage goals and checker’s definitions.
  • Testbench/environment creation: As per the DUT we need to create the interfaces, driver, monitor, agents, and create the environment as per requirements.
  • Writing Tests: This step involves writing sequences and tests for each feature as specified in the plan.
  • Writing checkers/assertions: in this step, we need to create a model or checkers/assertions. To check the expected behavior of the DUT and if the actual response of the DUT is matching with the expected response.
  • Coverage analysis: The goal of this step is to analyze code coverage and functional coverage and meet the 100% coverage.

Que 16: What it mean that functional coverage is 100% and code coverage is not 100%? and what can we do to meet a 100% coverage goal?
Ans 16:
There might be several possibilities to have 100% functional coverage and not 100% code coverage. Functional coverage tells us what kind of stimulus, configuration, and all the combinations of possible features have been covered but code coverage tells us how much code is exercised by the test cases. So the possibilities are :
There might be a missing feature in the functional coverage plan. This can be fixed using updating features or cross features in the Verification plan.
There is some redundant/unreachable code in the design. This can be excluded from the code coverage goal.

Que 17: What It mean that code coverage is 100% and functional coverage is not 100%? and what can we do to meet a 100% coverage goal?
Ans 17:
Yes, there are several possibilities to have 100% code coverage and not 100% functional coverage :
There are some features which is missing in the design implementation. We can ask the designer to implement the code.
Some of the sequence/property may not be getting cover. We can write more test cases to hit those sequences or modify those sequences if it is unreachable.

Que 18: what are the properties of object-oriented programming? Explain each property.
Ans 18:
System Verilog introduces classes as the foundation of the testbench automation language.
A class is a user-defined data type. Classes consist of data (called properties) and tasks and functions to access the data (called methods).
In System Verilog, classes support the following aspects of object-orientation:
Encapsulation(Data hiding): In System Verilog, we can define how properties and methods are visible/access to the other class. By default, all the members of the class have public access. This can be changed by local and protected keyword. “Local” data/methods can only be access within the same class and “protected” data/methods can be use by the same class or extended class only.
Inheritance: Inheritance is the ability to create new classes that are based on existing classes. A derived class by default inherits the properties and methods of its parent class.
However, the derived class may add new properties and methods, or modify the inherited properties and methods.
Polymorphism: Polymorphism in System Verilog provides an ability to an object to take on many forms. Method handle of super-class can be made to refer to the subclass method, this allows polymorphism or different forms of the same method. We use the keyword “virtual”, virtual data/methods can be changed or override in the extended class.

Que 19: What is the difference between Logic and Reg?
Ans 19:
Reg is a data storage element in System Verilog. It’s not an actual hardware register but it can store values. Reg retains its value until the next assignment statement. System Verilog added this additional datatype, It extends the reg/wire type so it can be driven by a single driver such as gate or module. The main difference between logic datatype and reg/wire is that a logic datatype can be driven by both continuous assignment, or blocking/non-blocking assignment.

Que 20: What are the features you will verify for a FIFO?
Ans 20:
We need to verify the following features for a FIFO verification :
We need to verify if we can verify “write” and “read” of the FIFO.
We need to verify the FIFO depth by writing the number of bytes equal to the depth.
We need to verify FIFO full and FIFO empty conditions to hit corner cases.
We need to verify the reset condition of the FIFO.

<< Previous | Next >>


Que 1: What is the difference between Verilog and System Verilog?
Ans 1:

– Verilog is an HDL(Hardware Description Language) while System Verilog(SV) is both HDL and HVL(Hardware Verification Language).
– Verilog has mainly 2 data types Reg and Wire which are 4-state logic 0, 1, x, and z, while SV is enriched with a wide variety of data types like int, shortint, longint, logic, bit, real, realtime, reg, user-defined data type, etc which are both combination of 4 and 2 valued logic.
– Memories and arrays declaration on Verilog are static in nature while in the case of SV, it’s dynamic in nature means declaration can be changed during compile time.
– The whole event queue in Verilog is subdivided into 4 regions which are active, inactive, NBA, and postponed regions while in the case of SV, it is divided into 17 regions and the introduction of program block which has an inbuilt method race-free testbench and used as a separation between DUT and TB unlike Verilog.
– FSM implementation in SV is much easier in SV with the use of an enum data type that has a number of methods like number, first, last, next, and previous which helps in debugging purposes unlike using parameters in Verilog which is hard coded.
– System Verilog uses interface construct which is used for bunching of all the signals along with clocking block which is used for synchronization, unlike Verilog in which instantiation with the DUT becomes tedious because of a large number of signals.
– Verilog uses a module-level testbench while SV uses a class based testbench which is dynamic in nature.

Que 2: When we can say the verification of a DUT is completed?
Ans 2:
In the beginning of the verification phase, we need to define the verification plan, which lists all the features needed to cover, functional coverage. Once all the features get verified and we achieve 100% functional coverage, Apart from these we need to achieve 100% code coverage. If we achieve all these conditions we can say verification of a DUT is completed.

Que 3: What is the difference between functional coverage and code coverage?
Ans 3:
Code coverage measures how much of the “design Code” is exercised. This includes the execution of design blocks, Number of Lines, Conditions, FSM, Toggle, and Path. The simulator tool will automatically extract the code coverage from the design code. Functional coverage is a user-defined metric that measures how much of the design specification has been exercised in verification.
There are two types of functional coverage,
Data-oriented Coverage – Checks combinations of data values that have occurred. We can get Data-oriented coverage by writing Coverage groups, and coverage points and also by cross-coverage
Control-oriented Coverage – Checks whether sequences of behaviors have occurred. We can get assertion coverage by writing System Verilog Assertions.

Que 4: What is constraint random verification?
Ans 4:
Constrained Random Verification (CRV) is a methodology that is supported by System Verilog which has a built-in constraint solver. This allows you to constrain your stimulus to better target a design function, thereby allowing you to reach your coverage goal faster with accuracy. From that sense, coverage and CRV go hand in hand. You check your coverage and see where the coverage holes are. You then constrain your stimulus to target those holes and improve coverage.

Que 5: What is the need for regression, what kind of tests are included in regression?
Ans 5: Regression is the method to run multiple tests together which was previously passed, It includes both random test cases and directed test cases. The regression run ensures the changes in design don’t impact the functionality. We need to keep running regression on a regular basis whenever there are design changes.

Que 6: What is the difference between “rand” and “randc” keywords?
Ans 6:
“rand” is a standard System Verilog keyword for random variables. This variable randomize with different values defined in range or constraint and it is uniformly distributed over the range until defined in constraint. “randc” is a keyword for the random cyclic variable that randomly iterates over all the values in the range and no value is repeated within an iteration until every possible value has been assigned.

Que 7: What is the difference between function and task?
Ans 7:
Functions: It cannot have time-controlling statements or delays, and executes in the same simulation time unit. It cannot enable a task. The function should have at least one input argument and cannot have output or inout arguments. It can return only a single value.
Task: It can have time-controlling statements or delay and completes at some other time. It can enable other tasks and functions. It can have zero or more arguments of any type. It cannot return a value but can achieve the same effect using output arguments.

Que 8: What is the virtual interface? How it is different from real interface?
Ans 8:
A virtual interface is a pointer to an actual interface in System Verilog. It is most often used in classes to provide a connection point to allow classes to access the signals in the interface through the virtual interface pointer.
An interface is a bundle of signals or nets through which a testbench communicates with a design. A virtual interface is a variable that represents an interface instance.

Que 9: Why do we need a virtual interface?
Ans 9:
The System Verilog interface is static in nature, whereas classes are dynamic in nature. because of this reason, it is not allowed to declare the interface within classes, but it is allowed to refer to or point to the interface. A virtual interface is a variable of an interface type that is used in classes to provide access to the interface signals.

Que 10: Can we generate the clock of 30Mhz in System Verilog? if yes, write the code to generate a 30MHz clock.
Ans 10:
If we calculate the time period of 30MHz we will get 33.333ns, which is an infinite fraction, which can not be represented in the System Verilog variable. Hence, a 30MHz clock is not possible to generate in System Verilog.

<< Previous | Next >>


Que 16: There are 100 water bottles. One of the bottles contains poisoned water. If a rat drinks poisoned water he will die after one hour of it. You have 1 hour to find out which bottle has the poison. How many minimum rats are needed to figure out which bottle contains poison?
Ans 16:
We can use digital logic to find out the poisoned bottle. Also, the rat will die in 1 hour and we have only 1 hour to figure it out we can give that water to rat only once. If we use the digital logic 100 numbers can be represented in 8 bits. If we convert each number into a digital number and give the water to those rats only if that position contains 1. Suppose the poison is in the 10th (00001010)bottle we will give the water to the 2nd and 4th rats. After 1 hour, we check which rats have died(represent logic 1) and which have not died(represent logic 0) and we can form back the number and we can figure it out. So, we need 8 rats to figure out the poisoned water bottle.

Que 17: You have a box with 10 pairs of blue socks, 10 pairs of black socks, and 10 pairs of gray socks of the same size. You can pick one sock at a time. How many times do you have to pick the socks from the box to ensure that you have at least one pair of socks with the same color?
Ans 17:
You have a total of 30 pairs of socks. If you pick 30 socks there might be a chance that all the socks are of the same leg. So, if we pick 1 more sock It will ensure that we will have a pair of socks. So we need to pick 31 socks from the box.

Que 18: You have a rectangular sheet with a circular hole anywhere in the sheet, you know the center of the sheet and the center of the hole, How will you divide the sheet into two parts such that their areas are equal?
Ans 18:
If we draw a straight line from the center of the rectangle in any direction it will divide the rectangle into 2 equal halves and the same in the circle. So we can draw a line that passes through the center of both rectangle and circle. This line will divide the sheet into two parts with equal area.

Que 19: You have a balance scale, You need to measure integer weights from 1kg. to 40kgs. only. How many minimum numbers of weights do you need if you can put weights on one side of the scale?
Ans 19:
We have weights that add up to 40 kg. we have 2 choices either we put it on balance or won’t put it. Hence, we can use binary weights which can count from 1 to 40. So the weights will be 20, 21, 22, 23, 24, 25 which is 1, 2, 4, 8, 16, 32. A total of 6 weights are needed.

Que 20: In the previous question, what is the minimum number of weights needed if you can put your weights on both sides of the scale.
Ans 20:
In this question, we can put the weights on either side of the balance scale or don’t put them on the scale. So, you will have 3 options +1, 0, or -1. We can use base 3 combinations of the weights 30, 31, 32, 33 which is 1, 3, 9, 27. A total of 4 weights are needed.

<< Previous | Next >>


Que 11: Calculate the number of squares in an 8×8 chessboard.
Ans 11: To calculate the number of squares in an 8×8 chessboard, we will calculate first with smaller numbers like 2×2 and 3×3.
In 2×2 there will be 4+1 = 5 squares.
In 3×3 there will be 9+4+1 = 14 squares.
In 4×4 there will be 16+9+4+1 = 30 squares.
Following the pattern we can calculate for 8×8 chessboard will be 64+49+36+25+16+9+4+1 = 204

Que 12: you have a 3 liter and a 5 liters buckets (Assume unlimited water source available). How will you measure 4 liters of water.
Ans 12:
We can follow the below sequence to get 4 liters of water. We can make the combination of 5 + 5 – 3 – 3 = 4 ltr. Refer to Table 6 for the sequence of activity.

Que 13: Find the angle between the minute and hour hands of the clock at 4:20 PM.
Ans 13:
First calculate the position of the minute hand w.r.t. 12 o’clock at 20 min. = (20*360o/60) = 120o. Then we can calculate the position of hour hand w.r.t 12 o’clock at 4:20 PM, we can write it as 420/60 = 41/3 = 13/3. To convert into the angle (13/3×360o / 12 ) = 130o. The Angle formed by the hour and minute hand will be 10o.

Que 14: You have two sand timers, which can show 4 minutes and 7 minutes respectively. Use both the sand timers(at one time or one after another or any other combination) and measure a time of 9 minutes.
Ans 14: Start the 7-minute sand timer and the 4-minute sand timer.
Once the 4-minute sand timer ends turn it upside down instantly.
Once the 7-minute sand timer ends turn it upside down instantly.
After the 4-minute sand timer ends turn the 7-minute sand timer upside down(it has now a minute of sand in it) So effectively 8 + 1 = 9.

Que 15: You have 9 balls, 8 of which have the same weight. The remaining one is defective and heavier than the rest. You can use a balance scale to compare weights to find which is the defective ball. How many measurements do you need so that you will be surely able to do it?
Ans 15:
We can split the balls into 3 groups with 3 balls in each group. Then we can compare any 2 groups if they are equal then defective ball is in the 3rd group or it will be in the heavier group. Then we will get 3 balls in which 1 is heavier, again we can compare 2 balls if they are equal 3rd ball is defective else heavier ball. So, in total, we need to measure 2 times to find out heavier balls.

<< Previous | Next >>


Que 6: You have two non-uniform threads, each takes 30 mins to burn if we burn it from one side. How will you measure 45 minutes with those two threads without cutting or breaking them?
Ans  6: If we burn it from one side, it will take 30 mins. to burn. So if we burn it from both the side it will burn in 15 mins. So, to measure 45 mins. 1st we will burn one thread from one side for 30 mins and immediately after it we will burn 2nd thread from both sides to measure 15 mins. and thus we can measure 45 mins.  

Que 7: You have 10 packets of chocolate, each packet consists of 10 chocolates. Each chocolate is 10gm except in one packet which has 11gms chocolate each, all the packets look similar. Use a digital weighing machine once to find out which packet has 11 gm of chocolates.
Ans  7: As we can use the weighing machine once, we have to make some combination of the chocolates in such a way that one weigh will tell the packet. One such possible combination is to take 1 chocolate from the 1st packet, 2 chocolate from the 2nd packet, and so on.
So, the total chocolates become 550gm. If 1st packet has the 11gm chocolate the measured weight will be 560gm. Likewise, if the nth packet has 11 gm chocolate measured weight will be (550+10n)gm.

Que 8: If a Pen and a pencil cost Rs 10, if the price of a pen is Rs 9 more than that of a pencil. What is the cost of a pen and pencil? 
Ans  8:
Suppose the price of the Pen is x and the price of the pencil is y.
             By the question  x + y = 10 and x – y = 9
             Solving both equations x(Pen) will be Rs 9.5 and y(Pencil) will be Rs 0.5. 

Que 9: There are 25 horses. You can conduct a race among at most 5 to find out their relative speed. At no point, you can find out the actual speed of the horse in a race. Find out how many races are required to get the top 3 fastest horses.
Ans  9: Make 5 groups of 5 horses and run 5 races. Suppose five groups are a,b,c,d, and e and the next alphabet represents its rank in the group(of 5 horses) eg. d3 means horse in group d and has ranked 3rd in his group. [ 5 RACES DONE ] 
a1 b1 c1 d1 e1 
a2 b2 c2 d2 e2 
a3 b3 c3 d3 e3 
a4 b4 c4 d4 e4 
a5 b5 c5 d5 e5 

Now make a race of (a1,b1,c1,d1,e1).[RACE 6 DONE] suppose result is a1>b1>c1>d1>e1 
which implies a1 must be FIRST. 
b1 and c1 MAY BE(but not must be) 2nd and 3rd. 
For the II positions, the horse will be either b1 or a2.
(we have to find the top 3 horses therefore we choose horses b1,b2,a2,a3, and c1 to race among them [RACE 7 DONE]. 
The only possibilities are : 
c1 may be third 
b1 may be the second or third 
b2 may be third 
a2 may be the second or third 
a3 may be third 
The final result will give ANSWER. suppose result is a2>a3>b1>c1>b2 
then answer is a1,a2,a3,b1,c1. 

Que 10: Prove that the number between 2 consecutive odd prime numbers(eg 17 19), is always divisible by 6.
Ans  10: To prove this, we need to prove that the number between two consecutive odd prime numbers is divisible by 2 and 3.
The number between two odd numbers will be even so it will be divisible by 2.
In each consecutive 3 odd number 1 number is always divisible by 3,  let’s say two consecutive odd prime numbers are n and n+2, then n-2 and n+4 will be divisible by 3 and hence the number between them n+1 will also be divisible by 3.

<< Previous | Next >>


Que 1: There are few bacteria in a bottle which gets double every day. On the 10th day, that bottle gets full. On which day the bottle was one-fourth.
Ans  1:  If the bacteria is double each day and on the 10th day, the bottle is getting full it means, It was half on the 9th day and one-fourth on the 8th day.

Que 2: 100 coins are lying on a table. 10 of them are heads up and 90 are tails up. You can’t see and feel the coins. How can we split the coins into two piles such that there is the same number of heads up in each pile?
Ans  2: We can make 2 piles of 10 and 90. Suppose if x coins are heads and 10-x tails on the 1st pile then it means there are 10-x heads are there in the 2nd pile. If we flip all the coins in 1st pile, then there will be 10-x heads up which will be equal to heads in 2nd pile.

Que 3: Four persons want to cross a bridge. They take 1min., 2min., 5min. and 10min. to cross the bridge respectively. If only two people can cross the bridge at a time and they need a torch. They have only one torch, so each time they cross they have to bring back that torch. Both the person crossing the bridge should have to walk together. In how much minimum time they all will cross the bridge?
Ans  3: Suppose we have persons a, b, c, and d which take 1min., 2min, 5min. and 10min. to cross the bridge respectively. We will follow the following sequence :

a and b cross the bridge:  2min.
a will return back:              1min.
c and d cross the bridge:   10 min.
b will return back:              2min.
a and b cross the bridge:    2min.
So in total 17 min. they all will cross the bridge.

Que 4: There are three closed boxes. There are apples in one box, oranges in 2nd box, and mixed fruit (apple and orange) in 3rd box. By mistakenly the labels of the items are incorrectly tagged on all the boxes. You can draw any one fruit from any box and label them correctly. 
Ans  4: Pick a fruit from the basket labeled ‘Mix fruit’. We know from the question that this basket does not contain ‘Mix fruit’ in that box.

If this fruit is an apple, then label this Basket as ‘Apple’. Now we’ve determined that the basket labeled as ‘Mix fruit’ only contains Apples.

The basket labeled as ‘Oranges’, but we know that since the label is incorrect, this basket either has only apples in it or has Mix fruit. Since we already know which basket contains only apples, we know that the basket labeled as ‘Oranges’ contains ‘Mix fruit’. So label it as ‘Mix fruit’. The 3rd basket will be labeled as ‘Oranges’.

Que 5: There are three persons at different places on a circular track, They start running in a random direction with the same speed, what is the probability that they will not cross each other?
Ans  5:
Each person can run in two directions clockwise or anticlockwise. So, all the people will have 2 options. So there will be a total of 8 possibilities in which they can run. They won’t cross each other if they all run in the same direction clockwise or anticlockwise. So, In 2 cases out of 8, they will not cross, Probability will be 2/8 = ¼.

<< Previous | Next >>

Digital Design

Que 6: What is the range of n bit 2’s complement and 1’s complement representation?

Ans  6: 2’s complement represents an integer in the range [−2n−1, 2n−1 − 1].
        1’s complement represents an integer in the range [−2n−1 + 1, 2n−1 − 1].

Que 7: In which two input gate, If we toggle any one of the inputs toggles the output?

Ans  7: In gray code, only one bit toggles in the next number, for every next number output should toggle, there could be two possibilities.
Refer to Table 1 for Possible solutions at Outputs 1 and 2.
This can be concluded that Output 1 is XOR and Output 2 is XNOR.

Que 8: In 7 input XOR gate, If 4 inputs are 1 and 3 inputs are 0, what will be the output?

Ans  8: In the XOR gate, When Input has even number of 1’s gives output 0 and if Odd number of inputs are 1 then output is 1.
If 4 inputs are 1 and 3 inputs are 0, then output will be 0.

Que 9: Which gates are universal gates? Design XOR gates using NAND gate.

Ans  9: A universal gate is a gate that can implement any Boolean function without the need to use any other gate type. The NAND and NOR gates are universal gates.
Refer to the Figure, for XOR gate implementation from the NAND gate.

Que 10: Implement OR gate using NAND gate.

Ans  10: OR gate can be converted to NAND gate using De Morgan’s theorem.
                A + B  = ((A + B )’)’
                = (A’ . B’)’
                Refer to the Figure, For OR gate using NAND gate implementation.

<< Previous | Next >>

Digital Design

Que 1: Prove that A+A'B = B+B'A = A+B.

Ans 1: A+A'B = (AB' + AB) + A'B
    = AB' + (AB + A'B)
    = AB' + B

A+A'B = (AB' + AB) + A'B
    = AB' + AB + AB + A'B
    = (AB' + AB ) + (AB + A'B)
    = A + B

Que 2: Convert 25.625 fraction decimal numbers into binary number system.

Ans  2: The weights in binary numbers are 25(32), 24(16), 23(8), 22(4), 21(2), 20(1), 2-1(.5), 2-2(.25), 2-3(.125) and so on.
25.625 can be written as 16+8+1+0.5+0.125, If the weight value exists it will
be mentioned as 1 else 0. So, 25.625 can be written as 11001.101.

Que 3: Convert 1011001 in 2’s complement and 1’s complement.

Ans 3: To convert binary numbers into 2’s complement, bits of binary numbers are inverted. So, 1011001 can be represented as 0100110 in 2’s complement.
To convert binary numbers into 1’s complement, Bits of the binary numbers are inverted except the last 1 in the binary number. So, 1011001 can be represented as 0100111 in 1’s complement.

Que 4: What is gray code representation and how to convert from binary number to gray code?

Ans  4: Gray code, is an ordering of the binary numeral system such that two successive values differ in only one bit. eg. 00, 01, 11, 10.
This representation can be used to reduce the combinational logic.
Refer the Fig. 1 for Gray code to binary code converter.

Que 5: Convert 10/3 into Base 3 system.

Ans 5: In base 3 system, weights of the number are 34(81), 33(27), 32(9), 31(3), 30(1), 3-1 (1/3), 3-2(1/9) and so on.
10/3 can be written as 9/3 +1/3 = 3 + 1/3, So the Base 3 representation of 10/3 would be 10.1.

<< Previous | Next >>