Que 1: What is the difference between Verilog and System Verilog?
Ans 1:

– Verilog is an HDL(Hardware Description Language) while System Verilog(SV) is both HDL and HVL(Hardware Verification Language).
– Verilog has mainly 2 data types Reg and Wire which are 4-state logic 0, 1, x, and z, while SV is enriched with a wide variety of data types like int, shortint, longint, logic, bit, real, realtime, reg, user-defined data type, etc which are both combination of 4 and 2 valued logic.
– Memories and arrays declaration on Verilog are static in nature while in the case of SV, it’s dynamic in nature means declaration can be changed during compile time.
– The whole event queue in Verilog is subdivided into 4 regions which are active, inactive, NBA, and postponed regions while in the case of SV, it is divided into 17 regions and the introduction of program block which has an inbuilt method race-free testbench and used as a separation between DUT and TB unlike Verilog.
– FSM implementation in SV is much easier in SV with the use of an enum data type that has a number of methods like number, first, last, next, and previous which helps in debugging purposes unlike using parameters in Verilog which is hard coded.
– System Verilog uses interface construct which is used for bunching of all the signals along with clocking block which is used for synchronization, unlike Verilog in which instantiation with the DUT becomes tedious because of a large number of signals.
– Verilog uses a module-level testbench while SV uses a class based testbench which is dynamic in nature.

Que 2: When we can say the verification of a DUT is completed?
Ans 2:
In the beginning of the verification phase, we need to define the verification plan, which lists all the features needed to cover, functional coverage. Once all the features get verified and we achieve 100% functional coverage, Apart from these we need to achieve 100% code coverage. If we achieve all these conditions we can say verification of a DUT is completed.

Que 3: What is the difference between functional coverage and code coverage?
Ans 3:
Code coverage measures how much of the “design Code” is exercised. This includes the execution of design blocks, Number of Lines, Conditions, FSM, Toggle, and Path. The simulator tool will automatically extract the code coverage from the design code. Functional coverage is a user-defined metric that measures how much of the design specification has been exercised in verification.
There are two types of functional coverage,
Data-oriented Coverage – Checks combinations of data values that have occurred. We can get Data-oriented coverage by writing Coverage groups, and coverage points and also by cross-coverage
Control-oriented Coverage – Checks whether sequences of behaviors have occurred. We can get assertion coverage by writing System Verilog Assertions.

Que 4: What is constraint random verification?
Ans 4:
Constrained Random Verification (CRV) is a methodology that is supported by System Verilog which has a built-in constraint solver. This allows you to constrain your stimulus to better target a design function, thereby allowing you to reach your coverage goal faster with accuracy. From that sense, coverage and CRV go hand in hand. You check your coverage and see where the coverage holes are. You then constrain your stimulus to target those holes and improve coverage.

Que 5: What is the need for regression, what kind of tests are included in regression?
Ans 5: Regression is the method to run multiple tests together which was previously passed, It includes both random test cases and directed test cases. The regression run ensures the changes in design don’t impact the functionality. We need to keep running regression on a regular basis whenever there are design changes.

Que 6: What is the difference between “rand” and “randc” keywords?
Ans 6:
“rand” is a standard System Verilog keyword for random variables. This variable randomize with different values defined in range or constraint and it is uniformly distributed over the range until defined in constraint. “randc” is a keyword for the random cyclic variable that randomly iterates over all the values in the range and no value is repeated within an iteration until every possible value has been assigned.

Que 7: What is the difference between function and task?
Ans 7:
Functions: It cannot have time-controlling statements or delays, and executes in the same simulation time unit. It cannot enable a task. The function should have at least one input argument and cannot have output or inout arguments. It can return only a single value.
Task: It can have time-controlling statements or delay and completes at some other time. It can enable other tasks and functions. It can have zero or more arguments of any type. It cannot return a value but can achieve the same effect using output arguments.

Que 8: What is the virtual interface? How it is different from real interface?
Ans 8:
A virtual interface is a pointer to an actual interface in System Verilog. It is most often used in classes to provide a connection point to allow classes to access the signals in the interface through the virtual interface pointer.
An interface is a bundle of signals or nets through which a testbench communicates with a design. A virtual interface is a variable that represents an interface instance.

Que 9: Why do we need a virtual interface?
Ans 9:
The System Verilog interface is static in nature, whereas classes are dynamic in nature. because of this reason, it is not allowed to declare the interface within classes, but it is allowed to refer to or point to the interface. A virtual interface is a variable of an interface type that is used in classes to provide access to the interface signals.

Que 10: Can we generate the clock of 30Mhz in System Verilog? if yes, write the code to generate a 30MHz clock.
Ans 10:
If we calculate the time period of 30MHz we will get 33.333ns, which is an infinite fraction, which can not be represented in the System Verilog variable. Hence, a 30MHz clock is not possible to generate in System Verilog.

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