Que 21: What are features you will verify for a Register?
Ans 21:
We need to verify the following features in a Register verification:

  • Reset values of the register.
  • We can write and read back the same value.
  • We can write hAA,h55, h00 andhFF data to ensure no connected bits.
  • Write to the register and backdoor read from a register to ensure writing at the same address.
  • Other features are clear on read and clear on write.

Que 22: How a UVM driver is connected with a UVM sequencer?
Ans 22:
The UVM driver class contains a TLM port called uvm_seq_item_pull_port which is connected to a uvm_seq_item_pull_export of UVM sequencer in the connect phase of a UVM agent.

Que 23: What is an analysis port? What is the use of an analysis port? What are the different types of analysis ports?
Ans 23:
Analysis port (class uvm_tlm_analysis_port) — a specific type of transaction-level port that can be connected to zero, one, or many analysis exports and through which a component may call the method write implemented in another component, specifically a subscriber.
port, export, and imp classes used for transaction analysis.
Broadcasts a value to all subscribers implementing a uvm_analysis_imp.
Receives all transactions broadcasted by a uvm_analysis_port.
Exports a lower-level uvm_analysis_imp to its parent.

Que 24: What are assertions? What are the different types of assertions?
Ans 24:
Assertions are used to check the behavior of a design, It is written in the form of properties that should be true throughout the simulation. Assert property is used to activate the property and cover property is used to check if the property is getting covered. There are two types of immediate assertions and concurrent assertions. Immediate Assertions: Immediate assertions are procedural statements and are mainly used in simulation. An assertion is basically a statement that something must be true, similar to the if statement. Concurrent Assertions: These validate the circuit behavior throughout the simulation, It gets evaluated based on the clock trigger.

Que 25: What is the use of the “dist” keyword in constraint? What is the difference between “:/” and “:=” symbols in constraints?
Ans 25:
The “dist” keyword is used for distribution in constraints. It is used when we need to assign different weights to the elements of random variables. eg.: A dist { 5 := 1; [10:12] := 2 ; [15:16] :/ 2 }
Two symbols used with dist keyword “:=” assign mention weightage to each element and “/=” assigns the mention weightage divided by the number of variables. In the above example, The weightage for each element will be 5 -> 1, 10 -> 2, 11 -> 2, 12 -> 2, 15 -> 2/2, 16 -> 2/2.

Que 26: What is UVM? What is the advantage of UVM?
Ans 26:
UVM is a methodology used for functional verification.

  • Reusability through test bench
  • Plug & Play of verification Ips
  • Generic Testbench Development
  • Sequence-based stimulus generation
  • Vendor & Simulator Independent
  • Smart Test bench i.e. generate legal stimulus from pre-planned coverage plan
  • Support CDV –Coverage-Driven Verification
  • Support CRV –Constraint Random Verification
  • Register modeling

Que 27: What is the difference between “uvm_component” and “uvm_object”?
Ans 27:
“uvm_component” is used to construct the UVM environment fixed part. They are used to make testbench components that do not change throughout the simulation. Classes are registered with the factory using macro uvm_component_utils. “uvm_object” is used for UVM transient objects like uvm_seq_item, uvm_transaction, and uvm_sequence. The base class uvm_object is also used for configuration objects, i.e. classes that contain configuration data to configure uvm_components, sequences, etc. Classes are registered with the factory using macrouvm_object_utils.

Que 28: What is uvm_phase? What are the different phases in UVM?
Ans 28:
UVM phases act as a synchronizing mechanism in the simulation because phases are defined as callbacks, classes derived from uvm_component can perform useful work in the callback phase method. Different phases in UVM are :

  • build_phase
  • connect_phase
  • end_of_elaboration_phase
  • start_of_simulation_phase
  • run_phase
  • extract_phase
  • check_phase
  • report_phase

Sub-phases in run_phase are :

  • reset_phase
  • configure_phase
  • main_phase
  • shutdown_phase

Que 29: Which UVM phase is top-down, bottom–up & parallel?
Ans 29:
The build phase is top-down and the Run phase is a parallel phase as all the run phases run parallelly. All other phases are bottom-up.

Que 30: Which phase is the task/time-consuming phase?
Ans 30:
The run phase is a task in UVM, while all other phases are functions, so the only Run phase is a time-consuming phase.

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