Verilog Conditional Operator

The evaluation of a conditional operator shall begin with a logical equality comparison of expression1 with zero, termed the condition. If the condition evaluates to false (0), then expression3 shall be
evaluated and used as the result of the conditional expression. If the condition evaluates to true (1), then
expression2 is evaluated and used as the result.

result = expression1(condition) ? expression2 : expression3

For example:
The following example of a three-state output bus illustrates a common use of the conditional operator:
The bus called data is driven onto busa when drive_busa is 1. If drive_busa is 0, then an
value 8 is driven onto busa. Otherwise, busa is not driven.

wire [15:0] busa = drive_busa ? data : 16'b8;

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Verilog Shift Operators

There are two types of shift operators: the logical shift operators, << and >>, and the arithmetic shift operators, <<< and >>>. The left shift operators, << and <<<, shall shift their left operand to the left by the number by the number of bit positions given by the right operand. In both cases, the vacated bit positions shall be filled with zeroes. The right shift operators, >> and >>>, shall shift their left operand to the right by the number of bit positions given by the right operand. The logical right shift shall fill the vacated bit positions with zeroes.

For example —In this example, the reg result is assigned the binary value 0100, which is 0001 shifted to the left two positions and zero-filled.

module shift; 
reg [3:0] start, result; 
initial begin start = 1; 
result = (start << 2); 

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Verilog Reduction Operators

The unary reduction operators shall perform a bitwise operation on a single operand to produce a single-bit result. For reduction and, reduction or, and reduction xor operators, the first step of the operation shall apply the operator between the first bit of the operand and the second using below logic Tables.
The second and subsequent steps shall apply the operator between the 1-bit result of the prior step and the next bit of the operand using the same logic table.
Reduction unary and operator:

Reduction unary or operator:

Reduction unary exclusive or operator:

For example: below table shows the results of applying reduction operators on different operands-

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Verilog Bitwise Operators

The bitwise operators shall perform bitwise manipulations on the operands; that is, the operator shall
combine a bit in one operand with its corresponding bit in the other operand to calculate 1 bit for the result.

Below are the results for each possible combinations

1 Bitwise binary AND operator:

2. Bitwise binary OR operator:

3. Bitwise binary exclusive or operator

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Verilog Logical Operators

The operators logical and (&&) and logical or (||) are logical connectives. The result of the evaluation of a logical comparison shall be 1 (defined as true), 0 (defined as false), or, if the result is ambiguous, the unknown value (x). The precedence of && is greater than that of ||, and both are lower than relational and equality operators. 

A third logical operator is the unary logical negation operator (!). The negation operator converts a nonzero or true operand into 0 and a zero or false operand into 1. An ambiguous truth value remains as x.

Example 1—If reg alpha holds the integer value 237 and beta holds the value zero, then the following
examples perform as described:
regA = alpha && beta; // regA is set to 0
regB = alpha || beta; // regB is set to 1

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Verilog Equality Operators

All four equality operators shall have the same precedence.

For the logical equality and logical inequality operators (== and !=), if, due to unknown or high-impedance bits in the operands, the relation is ambiguous, then the result shall be a 1-bit unknown value (x). 

For the case equality and case inequality operators (=== and !==), the comparison shall be done just as it is in the procedural case statement (see 9.5). Bits that are x or z shall be included in the comparison and shall match for the result to be considered equal. The result of these operators shall always be a known value, either 1 or 0.

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Verilog Rational Operators

Relational operators are used for comparing values. They return a Boolean result indicating the relationship between the operands.
Definitions of rational operator shown in below table-

An expression using these relational operators shall yield the scalar value 0 if the specified relation is false or the value 1 if it is true. If either operand of a relational operator contains an unknown (x) or highimpedance (z) value, then the result shall be a 1-bit unknown value (x).

When one or both operands of a relational expression are unsigned, the expression shall be interpreted as a comparison between unsigned values. If the operands are of unequal bit lengths, the smaller operand shall be zero-extended to the size of the larger operand. 

When both operands are signed, the expression shall be interpreted as a comparison between signed values. If the operands are of unequal bit lengths, the smaller operand shall be sign-extended to the size of the larger operand. 

If either operand is a real operand, then the other operand shall be converted to an equivalent real value and the expression shall be interpreted as a comparison between real values.

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Verilog Operators and Operands

We will understand the various Verilog operators and operands, their types, and their applications in digital circuit design.
Verilog operators are symbols that represent computations or operations on operands. They are classified into several categories based on their functionality.

Arithmetic operators:
Arithmetic operators perform mathematical operations on operands. Common arithmetic operators in Verilog such as addition, subtraction, multiplication, division, and modulus.

reg [3:0] result;
reg [3:0] a = 3;
reg [3:0] b = 5;
always @* begin
    result = a + b;   // Addition
    result = a - b;   // Subtraction
    result = a * b;   // Multiplication
    result = a / b;   // Division
    result = a % b;   // Modulus

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Parameters do not belong to either the variable or the net group. Parameters are not variables; they are constants. There are two types of parameters: module parameters and specify parameters. It is illegal to redeclare a name already declared by a net, parameter, or variable declaration. 

Both types of parameters accept a range specification. By default, parameters and specify params shall be as wide as necessary to contain the value of the constant, except when a range specification is present.

For example: 
parameter msb = 7; // defines msb as a constant value 7 
parameter e = 25, f = 9; // defines two constant numbers 
parameter r = 5.7; // declares r as a real parameter 
parameter byte_size = 8, byte_mask = byte_size - 1; 
parameter average_delay = (r + f) / 2; 
parameter signed [3:0] mux_selector = 0;

Parameters represent constants; hence, it is illegal to modify their value at run time. However, module parameters can be modified at compilation time to have values that are different from those specified in the declaration assignment. This allows customization of module instances. A parameter can be modified with the defparam statement or in the module instance statement. Typical uses of parameters are to specify delays and width of variables.

local parameters are identical to parameters except that they cannot directly be modified by defparam statements.

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A one-dimensional array with elements of type reg is also called a memory. These memories can be used to model read-only memories (ROMs), random access memories (RAMs), and reg files. Each reg in the array is known as an element or word and is addressed by a single array index.

Array declarations examples:

Array declarations examples:
reg [7:0] mema[0:255]; // declares a memory mema of 256 8-bit // registers. The indices are 0 to 255 
integer inta[1:64]; // an array of 64 integer values

Assignment to above array elements-
mema = 0; // Illegal syntax- Attempt to write to entire array 
arrayb[1] = 0; // Illegal Syntax - Attempt to write to elements // [1][0]..[1][255] 
arrayb[1][12:31] = 0; // Illegal Syntax - Attempt to write to // elements [1][12]..[1][31] 
mema[1] = 0; // Assigns 0 to the second element of mema 
arrayb[1][0] = 0; // Assigns 0 to the bit referenced by indices // [1][0] 
inta[4] = 33559; // Assign decimal number to integer in array 
chng_hist[t_index] = $time; // Assign current simulation time to element addressed by integer index

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