Verilog Procedural assignments

The primary discussion of procedural assignments is in Procedural assignments<add link>. However, a description of the basic ideas in this clause highlights the differences between continuous assignments and procedural assignments.

As stated in Continuous assignments<add link>, continuous assignments drive nets in a manner similar to the way gates drive nets. The
expression on the right-hand side can be thought of as a combinatorial circuit that drives the net
continuously. In contrast, procedural assignments put values in variables. The assignment does not have
duration; instead, the variable holds the value of the assignment until the next procedural assignment to that variable.

Procedural assignments occur within procedures such as always, initial (see Structured procedures <add link>), task, and function(see Tasks and functions <add link>) and can be thought of as “triggered” assignments. The trigger occurs when the flow of execution in the simulation reaches an assignment within a procedure. Reaching the assignment can be controlled by conditional statements. Event controls, delay controls, if statements, case statements, and looping statements can all be used to control whether assignments are evaluated. topic Behavioral modeling <add link> gives details and examples.

Variable declaration assignment:
The variable declaration assignment is a special case of procedural assignment as it assigns a value to a
variable. It allows an initial value to be placed in a variable in the same statement that declares the variable.
The assignment shall be to a constant expression. The assignment does not have duration; instead, the
variable holds the value until the next assignment to that variable. Variable declaration assignments to an
array are not allowed. Variable declaration assignments are only allowed at the module level. If the same
variable is assigned different values both in an initial block and in a variable declaration assignment, the
order of the evaluation is undefined.

 Example 1—Declare two real variables, assigned to the values 2.5 and 300,000.
 real r1 = 2.5, n300k = 3E6;

 Example 2—Declare a time variable and realtime variable with initial values.
 time t1 = 25;
 realtime rt1 = 2.5;

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Verilog Continuous assignments

Continuous assignments shall drive values onto nets, both vector and scalar. This assignment shall occur
whenever the value of the right-hand side changes. Continuous assignments provide a way to model
combinational logic without specifying an interconnection of gates. Instead, the model specifies the logical expression that drives the net.

The net declaration assignment:.
The first two alternatives in the net declaration are discussed in Nets and variables(<add link>). The third alternative, the net declaration assignment, allows a continuous assignment to be placed on a net in the same statement that declares the net.
For example:
The following is an example of the net declaration form of a continuous assignment:

wire (strong1, pull0) mynet = enable ;

The continuous assignment statement:
The continuous assignment statement shall place a continuous assignment on a net data type. The net may be explicitly declared or may inherit an implicit declaration in accordance with the implicit declaration rules defined in Implicit declarations Assignments on nets shall be continuous and automatic. In other words, whenever an operand in the right hand expression changes value, the whole right-hand side shall be evaluated. If the new value is different from the previous value, then the new value shall be assigned to the left-hand side.

For example:
The following example describes a module with one 16-bit output bus. It selects between one of
four input busses and connects the selected bus to the output bus.

module select_bus(busout, bus0, bus1, bus2, bus3, enable, s);
 parameter n = 16;
 parameter Zee = 16'bz;
 output [1:n] busout;
 input [1:n] bus0, bus1, bus2, bus3;
 input enable;
 input [1:2] s;
 tri [1:n] data;
 // net declaration
 // net declaration with continuous assignment
 tri [1:n] busout = enable ? data : Zee;
 // assignment statement with four continuous assignments
 assign
 data = (s == 0) ? bus0 : Zee,
 data = (s == 1) ? bus1 : Zee,
 data = (s == 2) ? bus2 : Zee,
 data = (s == 3) ? bus3 : Zee;
 endmodule

The following sequence of events is experienced during simulation of this example:
a) The value of s, a bus selector input variable, is checked in the assign statement. Based on the value
of s, the net data receives the data from one of the four input buses.
b) The setting of data net triggers the continuous assignment in the net declaration for busout. If
enable is set, the contents of data are assigned to busout; if enable is 0, the contents of Zee are
assigned to busout.

Delays:
A delay given to a continuous assignment shall specify the time duration between a right-hand operand
value change and the assignment made to the left-hand side. If the left-hand references a scalar net, then the delay shall be treated in the same way as for gate delays; that is, different delays can be given for the output rising, falling, and changing to high impedance (see Gate- and switch-level modeling <add link>).

If the left-hand references a vector net, then up to three delays can be applied. The following rules determine
which delay controls the assignment:
— If the right-hand side makes a transition from nonzero to zero, then the falling delay shall be used.
— If the right-hand side makes a transition to z, then the turn-off delay shall be used.
— For all other cases, the rising delay shall be used.
Specifying the delay in a continuous assignment that is part of the net declaration shall be treated differently
from specifying a net delay and then making a continuous assignment to the net. A delay value can be
applied to a net in a net declaration, as in the following example:

wire #10 wireA;

This syntax, called a net delay, means that any value change that is to be applied to wireA by some other
statement shall be delayed for ten time units before it takes effect. When there is a continuous assignment in a declaration, the delay is part of the continuous assignment and is not a net delay. Thus, it shall not be added to the delay of other drivers on the net.

Strength:

The driving strength of a continuous assignment can be specified by the user.
A drive strength specification shall contain one strength value that applies when the value being assigned to the net is 1 and a second strength value that applies when the assigned value is 0. 

The following keywords shall specify the strength value for an assignment of 1:
supply1 strong1 pull1 weak1 highz1
The following keywords shall specify the strength value for an assignment of 0:
supply0 strong0pull0 weak0 highz0

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Verilog Assignments Introduction

The assignment is the basic mechanism for placing values into nets and variables. There are two basic forms of assignments:
— The continuous assignment, which assigns values to nets
— The procedural assignment, which assigns values to variables
There are two additional forms of assignments, assign/de-assign and force/release, which are called procedural continuous assignments.

An assignment consists of two parts, a left-hand side and a right-hand side, separated by the equals ( = )
character; or, in the case of nonblocking procedural assignment, the less-than-equals ( <= ) character pair.

The right-hand side can be any expression that evaluates to a value. The left-hand side indicates the variable to which the right-hand side value is to be assigned. The left-hand side can take one of the forms given in below Table, depending on whether the assignment is a continuous assignment or a procedural assignment.

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