Verilog Functions and function calling

A function definition shall begin with the keyword function, followed by the name of the function, followed either by a semicolon or by a function port list enclosed in parentheses and then a semicolon, and then shall end with the keyword endfunction.
Function inputs shall be declared one of two ways:
a) The first method shall have the name of the function followed by a semicolon. After the semicolon, one or more input declarations optionally mixed with block item declarations shall follow. After the function item declarations, there shall be a behavioral statement.

For example-

function [7:0] getbyte (input [15:0] address);
begin
       // code to extract low-order byte from addressed word
       . . .
getbyte = result_expression;
end
endfunction

b) The second method shall have the name of the function, followed by an open parenthesis and one or more input declarations, separated by commas. After all the input declarations, there shall be a close parenthesis and a semicolon. After the semicolon, there shall be zero or more block item declarations, followed by a behavioral statement.

For example-

function [7:0] getbyte (input [15:0] address);
begin
// code to extract low-order byte from addressed word
. . .
getbyte = result_expression;
end
endfunction

Function rules:

Functions are more limited than tasks. The following rules govern their usage:
a) A function definition shall not contain any time-controlled statements, that is, any statements containing #, @, or wait.
b) Functions shall not enable tasks.
c) A function definition shall contain at least one input argument.
d) A function definition shall not have any argument declared as output or inout.
e) A function shall not have any nonblocking assignments or procedural continuous assignments.
f) A function shall not have any event triggers.

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