Event data types

The event data type is an enhancement over Verilog named events. SystemVerilog events provide a handle to a synchronization object. Like Verilog, event variables can be explicitly triggered and waited for. Furthermore, SystemVerilog events have a persistent triggered state that lasts for the duration of the entire time step. In addition, an event variable can be assigned another event variable or the special value null. When assigned another event variable, both event variables refer to the same synchronization object. When assigned null, the association between the synchronization object and the event variable is broken. Events can be passed as arguments to tasks.

The syntax to declare an event is:

event variable_name [= initial_value];

Where variable_name is a valid identifier and the optional initial_value can be another event variable or the special value null.

If an initial value is not specified then the variable is initialized to a new synchronization object.

If the event is assigned null, the event becomes nonblocking, as if it were permanently triggered.


event E1;               // declare a new event called E1

event E2 = E1;  // declare E2 as alias to E1

event empty = null    // event variable with no synchronization object

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String data type

SystemVerilog includes a string data type, which is a variable size, dynamically allocated array of bytes.
SystemVerilog also includes a number of special methods to work with strings.

Verilog supports string literals, but only at the lexical level. In Verilog, string literals behave like packed arrays of a width that is a multiple of 8 bits. A string literal assigned to a packed array of an integral variable of a different size is either truncated to the size of the variable or padded with zeroes to the left as necessary.

In SystemVerilog string literals behave the same as in Verilog However, SystemVerilog also supports the string data type to which a string literal can be assigned. When using the string data type instead of an integral variable, strings can be of arbitrary length and no truncation occurs. Literal strings are implicitly converted to the string type when assigned to a string type or used in an expression involving string type operands.

Variables of type string can be indexed from 0 to N-1 (the last element of the array), and they can take on the special value “”, which is the empty string.

The syntax to declare a string is:

string variable_name [= initial_value];

where variable_name is a valid identifier and the optional initial_value can be a string literal or the value “”

for an empty string.

Example :
string myName = "John";

If an initial value is not specified in the declaration, the variable is initialized to “”, the empty string.

SystemVerilog provides a set of operators that can be used to manipulate combinations of string variables and string literals.

A string literal can be assigned to a string or an integral type. If their size differs the literal is right justified
and either truncated on the left or zero-filled on the left, as necessary.

Example :
byte c = "A"; // assign to c "A"
bit [10:0] a = "\x41"; // assigns to a ‘b000_0100_0001
bit [1:4][7:0] h = "hello" ; // assigns to h "ello"

A string, string literal, or packed array can be assigned to a string variable. The string variable shall grow or shrink to accommodate the packed array. If the size (in bits) of the packed array is not a multiple of 8, then the packed array is zero-filled on the left.

Example :
string s1 = "hello"; // sets s1 to "hello"
bit [11:0] b = 12’ha41;
string s2 = b; // sets s2 to ’h0a41

As a second example:

reg [15:0] r;
integer i = 1;
string b = "";
string a = {"Hi", b};

r = a;           // OK
b = r;           // OK (implicit cast, implementations can issue a warning)
b = "Hi";       // OK
b = {5{"Hi"}}; // OK
a = {i{"Hi"}}; // OK (non-constant replication)
r = {i{"Hi"}}; // invalid (non-constant replication)
a = {i{b}};     // OK
a = {a,b};      // OK
a = {"Hi",b};  // OK
r = {"H",""};  // yields “H\0” “” is converted to 8’b0
b = {"H",""};  // yields “H” “” is the empty string
a[0] = "h";    // OK same as a[0] = “hi” )


function int len()

  • str.len() returns the length of the string, i.e., the number of characters in the string (excluding any terminating character).
  • If str is “”, then str.len() returns 0.


task putc(int i, string s)
task putc(int i, byte c)

  •  str.putc(i, c) replaces the ith character in str with the given integral value.
  •  str.putc(i, s) replaces the ith character in str with the first character in s.
  •  s can be any expression that can be assigned to a string.
  •  putc does not change the size of str: If i < 0 or i >= str.len(), then str is unchanged.


function int getc(int i)

  •  str.getc(i) returns the ASCII code of the ith character in str.
  •  If i < 0 or i >= str.len(), then str.getc(i) returns 0.


function string toupper()

  • str.toupper() returns a string with characters in str converted to uppercase.
  • str is unchanged.


function string tolower()

  • str.tolower() returns a string with characters in str converted to lowercase.
  • str is unchanged.


function int compare(string s)

  • str.compare(s) compares str and s and embedded null bytes are included.


function int icompare(string s)

  • str.icompare(s) compares str and s, the comparison is case insensitive and embedded null bytes are included.


function string substr(int i, int j)

  • str.substr(i, j) returns a new string that is a substring formed by characters in position i through j of str.
  • If i < 0, j < i, or j >= str.len(), substr() returns ” ” (the empty string).

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System Verilog data types

2-state (two-value) and 4-state (four-value) data types

Types that can have unknown and high-impedance values are called 4-state types. These are logic, reg, integer, and time. The other types do not have unknown values and are called 2-state types, for example, bit and int.
The difference between int and integer is that int is 2-state logic and integer is 4-state logic. 4-state values have additional bits that encode the X and Z states. 2-state data types can simulate faster, take less memory, and are preferred in some design styles.

Signed and unsigned data types

Integer types use integer arithmetic and can be signed or unsigned. This affects the meaning of certain operators such as ‘<’, etc.

int unsigned ui;
int signed si;

The data types byte, shortint, int, integer, and longint default to signed. The data types bit, reg and logic default to unsigned, as do arrays of these types.
Note that the signed keyword is part of Verilog-2001. The unsigned keyword is a reserved keyword in Verilog- 2001, but is not utilized.

Real and shortreal data types

The real data type is from Verilog-2001 and is the same as a C double. The shortreal data type is a SystemVerilog data type and is the same as a C float.

Void data type

The void data type represents non-existent data. This type can be specified as the return type of functions, indicating no return value. This type can also be used for members of tagged unions

Integer data types

SystemVerilog offers several integer data types, representing a hybrid of both Verilog and C data types:

shortint :   2-state SystemVerilog data type, 16 bit signed integer
int :         2-state SystemVerilog data type, 32 bit signed integer
longint :    2-state SystemVerilog data type, 64 bit signed integer
byte  :       2-state SystemVerilog data type, 8 bit signed integer or ASCII character
bit  :        2-state SystemVerilog data type, user-defined vector size
logic  :      4-state SystemVerilog data type, user-defined vector size
reg  :        4-state Verilog-2001 data type, user-defined vector size
integer  :   4-state Verilog-2001 data type, 32 bit signed integer
time  :       4-state Verilog-2001 data type, 64-bit unsigned integer

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