Introduction of Verilog Tasks and functions

Tasks and functions provide the ability to execute common procedures from several different places in a
description. They also provide a means of breaking up large procedures into smaller ones to make it easier to read and debug the source descriptions. This topic discusses the differences between tasks and functions, describes how to define and invoke tasks and functions, and presents examples of each.

Difference between tasks and functions:

The following rules distinguish tasks from functions:
— A function shall execute in one simulation time unit; a task can contain time-controlling statements.
— A function cannot enable a task; a task can enable other tasks and functions.
— A function shall have at least one input type argument and shall not have an output or inout type
argument; a task can have zero or more arguments of any type.
— A function shall return a single value; a task shall not return a value.

The purpose of a function is to respond to an input value by returning a single value. A task can support
multiple goals and can calculate multiple result values. However, only the output or inout type arguments
pass result values back from the invocation of a task. A function is used as an operand in an expression; the value of that operand is the value returned by the function.

We will discussing more details about functions & calling function in below link-
Verilog function & function calling

More Details about Task & calling task can be find in below link-
Verilog task & calling

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Verilog Tasks and task enabling

There are two alternate task declaration syntaxes.

a) The first syntax shall begin with the keyword task, followed by a name for the task and a semicolon, and ending with the keyword endtask. Task item declarations can specify the following:
— Input arguments
— Output arguments
— Inout arguments
— All data types that can be declared in a procedural block

Example 1—The following example illustrates the basic structure of a task definition with five arguments:
task my_task;
input a, b;
inout c;
output d, e;
begin
. . . // statements that perform the work of the task
. . .
c = foo1; // the assignments that initialize result regs
d = foo2;
e = foo3;
end
endtask

b) The second syntax shall begin with the keyword task, followed by a name for the task and a parenthesis-enclosed task_port_list. The task_port_list shall consist of zero or more comma separated task_port_items.

task my_task (input a, b, inout c, output d, e);
begin
. . . // statements that perform the work of the task
. . .
c = foo1; // the assignments that initialize result regs
d = foo2;
e = foo3;
end
endtask

Task memory usage and concurrent activation:
A task may be enabled more than once concurrently, variables declared in static tasks, including input, output, and inout type arguments, shall retain their values between invocations.
Variables declared in automatic tasks, including output type arguments, shall be initialized to the default
initialization value whenever execution enters their scope. input and inout type arguments shall be
initialized to the values passed from the expressions corresponding to these arguments listed in the taskenabling statements.

Disabling of named blocks and tasks:
The disable statement provides the ability to terminate the activity associated with concurrently active
procedures, while maintaining the structured nature of Verilog HDL procedural descriptions.
The disable statement can be used within blocks and tasks to disable the particular block or task containing the disable statement. The disable statement can be used to disable named blocks within a function, but cannot be used to disable functions.

Example 1—This example illustrates how a block disables itself.
begin : block_name
rega = regb;
disable block_name;
regc = rega; // this assignment will never execute
end

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Verilog Functions and function calling

A function definition shall begin with the keyword function, followed by the name of the function, followed either by a semicolon or by a function port list enclosed in parentheses and then a semicolon, and then shall end with the keyword endfunction.
Function inputs shall be declared one of two ways:
a) The first method shall have the name of the function followed by a semicolon. After the semicolon, one or more input declarations optionally mixed with block item declarations shall follow. After the function item declarations, there shall be a behavioral statement.

For example-

function [7:0] getbyte (input [15:0] address);
begin
       // code to extract low-order byte from addressed word
       . . .
getbyte = result_expression;
end
endfunction

b) The second method shall have the name of the function, followed by an open parenthesis and one or more input declarations, separated by commas. After all the input declarations, there shall be a close parenthesis and a semicolon. After the semicolon, there shall be zero or more block item declarations, followed by a behavioral statement.

For example-

function [7:0] getbyte (input [15:0] address);
begin
// code to extract low-order byte from addressed word
. . .
getbyte = result_expression;
end
endfunction

Function rules:

Functions are more limited than tasks. The following rules govern their usage:
a) A function definition shall not contain any time-controlled statements, that is, any statements containing #, @, or wait.
b) Functions shall not enable tasks.
c) A function definition shall contain at least one input argument.
d) A function definition shall not have any argument declared as output or inout.
e) A function shall not have any nonblocking assignments or procedural continuous assignments.
f) A function shall not have any event triggers.

<<add the example of function with EDA>>

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System tasks and functions

This describes system tasks and functions that are considered part of the Verilog-AMS HDL. It
also states whether a particular system task or function is supported in the digital context and if it is supported in the analog context. The system tasks and functions are divided into various categories.

1). Display system tasks:

The display group of system tasks is divided into three categories: the display and write tasks, strobed
monitoring tasks, and continuous monitoring tasks.

$strobe ( list_of_arguments ) ; — It provides the ability to display simulation data when the simulator has converged on a solution for all nodes.
$display ( list_of_arguments ) ; — It provides the same capabilities as $strobe
$monitor ( list_of_arguments ) ; — It provides the ability to monitor and display the values of any variables or expressions specified as arguments to the task.
$debug( list_of_arguments ) ; — It provides the capability to display simulation data while the analog simulator is solving the equations; it displays its arguments for each iteration of the analog solver.

Escape sequences for printing special characters: The escape sequences shown in below Table, when included in a string argument, print special characters.

Escape sequences for format specifications: The special character % indicates that the next character should be interpreted as a format specification that establishes the display format for a subsequent expression argument.

2) File input-output system tasks and functions:

The system tasks and functions for file-based operations are divided into the following categories:
— Functions and tasks that open and close files
— Tasks that output values into files
— Tasks that output values into variables
— Tasks and functions that read values from files and load into variables or memories

Opening and closing files: $fopen and $fclose–

fd = $fopen ( ” file_name ” , type ) ;
$fclose ( fd ) ;

The function $fopen opens the file specified as the filename argument and returns either a 32-bit
multichannel descriptor or a 32-bit file descriptor determined by the absence or presence of the type
argument.
filename is a character string or is a reg containing a character string that names the file to be opened.

Types for file descriptors–

3) Simulation control system tasks:

There are two simulation control system tasks:
a) $finish [ ( n ) ]
b) $stop [ ( n ) ]

The $finish system task simply makes the simulator exit and pass control back to the host operating system. If an expression is supplied to this task, then its value (0, 1, or 2) determines the diagnostic messages that are printed before the prompt is issued as shown in below Table. If no argument is supplied, then a value of 1 is taken as the default.

The $stop system task causes simulation to be suspended. This task takes an optional expression argument (0, 1, or 2) that determines what type of diagnostic message is printed. The amount of diagnostic messages output increases with the value of the optional argument passed to $stop.


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